This invention relates to a clock control circuit and, more particularly, to a clock control circuit that employs an interpolator.
A PLL (Phase-Locked Loop) or a DLL (Delay-Locked Loop) is used as a clock control circuit for supplying a clock to a sequential circuit or circuit block driven by a clock. In addition, a combination of a PLL, DLL and interpolator also is known in the art.
Several examples of clock control techniques using interpolators will now be described. The generation of multiphase clocks P0 to Pn using a PLL circuit is described in Reference 1 (ISSC 1993 pp. 160-161, Mark Horowitz et al., xe2x80x9cPLL Design for a 500 MB/s Interfacexe2x80x9d). In an arrangement described in Reference 1, as shown in FIG. 16, a PLL 1510 outputs multiphase clock signals P0 to Pn synchronized to an input clock 1. The multiphase clock signals P0 to Pn are fed to a switch 1520. Two mutually adjacent signals (of even and odd phases) selected by the switch 1520 are provided to an interpolator (a phase interpolator) 1530, which produces an output signal OUT obtained by internally dividing the phase difference between these two input signals. The switch 1520 that selects the pair of signals provided to the interpolator 1530 comprises an even-phase selector, a shift register for supplying a selection control signal to the even-phase selector, an odd-phase selector and a shift register for supplying a selection control signal to the odd-phase selector.
In the arrangement described in Reference 1, the interpolator 1530 has an analog structure comprising a differential circuit that receives two inputs. A control circuit 1540 has an FSM (Finite State Machine) circuit for monitoring phase to determine which of the two inputs is earlier in phase and for outputting a count signal to an up/down counter (not shown), and a DA converter (not shown) for converting the output of the up/down counter to an analog signal. The DA converter supplies the interpolator 1530 with a current corresponding to the even/odd phase. The PLL 1520 comprises a phase comparator circuit, a loop filter, a voltage-controlled oscillator (VCO) to which the voltage of the loop filter is input as the control voltage, and a frequency divider for frequency dividing the output of the voltage-controlled oscillator and feeding the resultant signal back to an input of the phase comparator circuit.
Further, Reference 2 (ISSCC 1997 pp. 332-333, S. Sidiropoulos and Mark Horowitz et al., xe2x80x9cA semi-digital delay locked loop with unlimited phase shift capability and 0.08-400 MHz operating rangexe2x80x9d) describes an arrangement in which a DLL (Delay-Locked Loop) circuit is used instead of the PLL circuit of FIG. 16. Here a DLL outputs multiphase clock signals P0 to Pn synchronized to the input clock. The multiphase clock signals P0 to Pn are input to the selector (switch) 1520. Two mutually adjacent signals enter the interpolator 1520, which delivers the output signal OUT obtained by internally dividing the phase difference between these two signals. On the basis of the result of detecting a phase difference between the output OUT and a reference clock, the control circuit 1540 conducts control to vary the interior-division ratio of the interpolator 1530 and controls the switching of the selector 1520. The interpolator also is implemented by analog circuits.
In order to provide a clock control circuit that reduces phase error to a major degree by eliminating center-frequency fluctuation, which is caused when a PLL or the like is used, and jitter that is ascribable to a feedback loop, the Applicant has proposed a clock control circuit, which is described in the specification of Japanese Patent Application No. 2000-083579, that uses a frequency multiplying interpolator as multiphase clock generating circuit for generating the multiphase clock signals P0 to Pn.
Reference will be had to FIG. 14 to give an overview of this clock control circuit, which uses an interpolator, proposed in Japanese Patent Application No. 2000-083579 (still undisclosed at the time of filing of this application). Clock signals P0 to Pn generated using a frequency multiplying interpolator as a multiphase clock generating circuit 210 are adjusted to any phase by a clock selector 170 and a fine adjusting interpolator 130. As described in the specification of Japanese Patent Application No. 2000-083579, the frequency multiplying interpolator includes a frequency divider for frequency dividing an input clock to thereby generate and output multiphase clocks; a cycle sensing circuit for sensing the cycle of the input clock, and a multiphase-clock frequency multiplying circuit, which has the multiphase clocks output by the frequency divider input thereto, for generating multiphase clocks obtained by frequency multiplying these multiphase clocks. The multiphase-clock frequency multiplying circuit has a plurality of timing-difference dividing circuits each for outputting a signal obtained by dividing a timing difference between two inputs applied thereto, and a plurality of multiplexing circuits each for multiplexing and outputting output signals from two timing-difference dividing circuits. Each of the plurality of timing-difference dividing circuits has a timing-difference dividing circuit (interpolator) to which two identical-phase clocks are applied as inputs and a timing-difference dividing circuit to which two clocks of mutually adjacent phases are applied as inputs. In the present invention, the multiphase clock generating circuit 210 is not limited to a frequency multiplying interpolator; any suitable arrangement may be used. A detailed description of the frequency multiplying interpolator proposed by the aforesaid Japanese Patent Application No. 2000-083579 is not included in the specification of this application.
On the basis of a control signal S (referred to as a xe2x80x9cclock selection signalxe2x80x9d) output from the control circuit 200, the clock selector 170 selects mutually adjacent odd- and even-phase signals as a signal pair from the multiphase clock signals P0 to Pn output by the multiphase clock generating circuit 210, and supplies these signals to the interpolator 130.
On the basis of a control signal C and its complementary signal CB output from the control circuit 200, the interpolator 130 outputs a signal of a propagation delay tpd, which is defined by a time obtained by internally dividing the phase difference (timing difference) between two input signals applied thereto.
The control circuit 200 has a shift register (not shown) as a circuit for supplying the interior-division ratio control signal C/CB to the interpolator 130. Upon receiving an output signal (the result of a phase comparison) from a phase comparator that compares the phase of a reference clock (not shown) and the phase of the output clock from the interpolator 130, the control circuit 200 outputs the interior-division ratio control signal C/CB, which is for varying the timing-difference division value (interior-division ratio) of the timing difference between the two inputs to the interpolator 130, in order to compensate for phase lead/lag in accordance with the degree of phase lead/lag of the output of interpolator 130 with respect to the reference clock. An arrangement may be adopted in which the control signal CB, which is the complement of the interior-division ratio control signal C, is not generated in the control circuit 200. Rather, a signal obtained by inverting each control signal C, which is output from the control circuit 200, by an inverter, may be supplied to the interpolator 130 as the signal CB.
Further, the control circuit 200 has a counter and a decoder (neither of which are shown) as the circuit for supplying the clock selection control signal S to the clock selector 170. If, when it is detected that the setting of the interior-division ratio of the interpolator 130 has reached an upper or lower limit (extremal point), it is necessary to adjust further the lead/lag of the output clock of interpolator 130 with respect to the reference clock, the set range of the interior-division ratio is switched over to a different range. In order to accomplish this, the control circuit 200 changes over the set value of the clock selection control signal S, which is output to the clock selector 170, in dependence upon phase lead or lag. The clock selector 170 responds to the clock selection control signal S, the value of which has been changed over, by changing over clock-pair combination output to the interpolator 130.
For example, assume that the clock selector 170 selects the set of clocks P1 and P2 from among the multiphase clocks P0 to Pn [where the phase difference between clocks is 360xc2x0/(n+1)], and that it is necessary to further advance the phase of the output signal of interpolator 130 from the phase difference between the output signal of interpolator 130 and the reference signal (reference clock). In such case the clock selector 170, upon receiving the clock selection control signal S from the control circuit 200, changes over the clock output, and supplies it to the interpolator 130, so as to internally divide the phase difference (timing difference) between, say, the clock signal P0, the phase of which is one advanced than that of the presently selected clock signal P1 (where Pxe2x88x921 is assumed to be Pn), and the original clock signal P1. On the other hand, in a case where it is necessary to regard further the phase of the output of interpolator 130, the clock selector 170, upon receiving the clock selection control signal S from the control circuit 200, changes over the clock signal pair, and supplies it to the interpolator 130, so as to internally divide the phase difference (timing difference) between the clock signal P3, the phase of which is one later than that of the presently selected clock signal P2 (where Pn+1 is assumed to be P0), and the original signal P2.
Let the suffix n of the multiphase clocks be 2mxe2x88x921 (the number of phases of the multiphase clocks is 2m). The clock selector 170 includes a first selector (not shown) which, in response to the clock selection control signal S from the control circuit 200, selects one of the odd-phase clocks P0, P2, P4, xc2x7 xc2x7 xc2x7 , 2mxe2x88x922, and a second selector (not shown) which, in response to the clock selection control signal S from the control circuit 2300, selects one of the even-phase clocks P1, P3, P5, xc2x7 xc2x7 xc2x7 , 2mxe2x88x921. The control circuit 200 performs control to change over the clock output in such a manner that the combination of the odd-, even-phase clock output pair supplied to the interpolator 130 will be a clock pair of mutually adjacent odd- and even-phase clocks, e.g., (P0, P1), (P2, P1), (P2, P3) and so on.
As mentioned above, the control circuit 200 in the clock control circuit of FIG. 14 includes a counter and a decoder circuit for supplying the clock selector 170 with the clock selection control signal S. If the number of phases of the multiphase clocks becomes too large, this will lead to an increase in the size of the decoder circuit. The Inventor has recognized that the decoder circuit, etc., needs to be specially contrived.
The inventor has recognized also that it is necessary to implement a control circuit that is reduced in size and that is resistance to error ascribable to noise and the like.
Accordingly, it is an object of the present invention to provide a clock control circuit the size of which is reduced.
The above and other objects of the invention are satisfied, at least by providing a clock control circuit, in accordance with one aspect of the present invention, which comprises:
a ring counter, in which counting direction changes over freely between up and down directions, for outputting 2N-number of N-bit signals and N-bit inverted signals, which are obtained by inverting each bit of the N-bit signals, as count values;
a decoder circuit, which receives a 2N-bit signal comprising the N-bit signal and the N-bit inverted signal output from the ring counter, for inverting one bit of the 2N-bit signal to thereby output a decoded signal in which at least two mutually adjacent bits among the 2N bits take on a first value and the other bits take on a second value, the 2Nth bit and the first bit at the ends of the 2N-bit signal being mutually adjacent;
a clock selector, which receives a plurality of clock signals of mutually shifted phases are input and which receives the decoded signal output from the decoder circuit as a clock selection control signal, for outputting a pair of clock signals selected from the plurality of clock signals;
an interpolator, which receives the pair of clock signals output from the clock selector from first and second input terminals, for outputting, from an output terminal, a clock signal having a delay time corresponding to a time obtained by internally dividing a phase difference between the pair of clock signals at an interior-division ratio set by an interior-division control signal input thereto; a phase comparator circuit for comparing phase of the clock signal, which is output from the interpolator, and phase of a reference clock; and
an interpolator control circuit, which receives a phase-comparison result signal output from the phase comparator circuit, and which comprises a shift register the shift direction of which is varied based upon the phase-comparison result signal and a forward/reverse relationship of the phases of the clock signals input to the first and second input terminals of the interpolator, for supplying the interpolator with the interior-division control signal that sets the interior-division ratio of the interpolator.
In accordance with another aspect of the present invention, the interpolator control circuit has a circuit which, in a case where the interior-division ratio of the interpolator has attained an upper-limit value or a lower-limit value (referred to as an xe2x80x9cextremal pointxe2x80x9d), places a flag signal, which is indicative of an extremal point, in an active state and outputs the active signal. The clock control circuit further includes a circuit for generating up and down signals, which are supplied to the ring counter, based upon the phase-comparison result signal from the phase comparator circuit when the flag signal output from the interpolator control circuit indicative of the extremal point is active.
In accordance with another aspect of the present invention, the ring counter is provided with N-number of flip-flops and N-number of logic circuits, Which correspond to respective ones of the N-number of flip-flops, for supplying input signals to respective ones of these flip-flops; each logic circuit having an up signal, a down signal and a hold signal specifying up, down and hold, respectively, and an output signal from each of the N-number of flip-flops input thereto; control being performed in such a manner that: in the case of an up-count, a signal that is the inverse of the output of the last flip-flop is fed back and input to the first flip-flop via the logic.circuit corresponding to the first flip-flop, the state of the output of the preceding flip-flop being transmitted to the input of the succeeding flip-flop via each logic circuit at the time of a shift operation by the clock; in the case of a down-count, a signal that is the inverse of the output of the first flip-flop is fed back and input to the last flip-flop via the logic circuit corresponding to the last flip-flop, the state of the output of the succeeding flip-flop being transmitted to the input of the preceding flip-flop via each logic circuit at the time of a shift operation by the clock; and in the case-of the hold state, the output signals of the flip-flops corresponding to the logic circuits are supplied to the inputs of the flip-flops corresponding to the logic circuits.
In the present invention, the decoder circuit is preferably composed by 2N-number of AND gates the inputs to which are an Ith bit and an (I+1)th bit (where I is 1, 2, xcx9cN, and 2N+1 becomes 1 when I is 2N) of a signal, which has a bit width of 2N, comprising the N-bit signal and the signal obtained by inverting each bit of this N-bit signal.
In the present invention, the interpolator control circuit has a plurality of unit circuits each of which outputs an interior-division control signal that sets the interior-division ratio of the interpolator, the output of the unit circuit that is at one end of the plurality of unit circuits being transmitted as the output of the unit circuit at the other end in domino fashion.
More specifically, the interpolator control circuit has at least a plurality (M-number) of flip-flops; a control signal generating circuit for generating left-shift, right-shift and hold signals based upon the up signal and down signal output from the phase comparator circuit and the value of the flag signal output from the flag generating circuit; and M-number of control logic circuits; wherein (Mxe2x88x922)-number of the control logic circuits exclusive of the first and Mth thereof at both ends have, as inputs thereto, the left-shift, right-shift and hold signals output from the control signal generating circuit, an output signal corresponding to each control logic circuit from among the M-bit output signals, and two output signals neighboring this output signal, for deciding, and supplying to a data input terminal of the corresponding flip-flop, an output logic value in accordance with the value of each output signal input thereto and the shift direction; the first and M-th control logic circuits have, as inputs thereto, the left-shift, right-shift and hold signals output from the control signal generating circuit, output signals corresponding to respective ones of the control logic circuits at the ends, one output signal neighboring this output signal, and a fixed potential, for deciding, and supplying to a data input terminal of the corresponding flip-flop, an output logic value in accordance with these output signals and the shift direction; an output of each flip-flop exclusive of the first flip-flop is provided with an OR gate; and each OR gate, which receives the output signal of the flip-flop preceding the corresponding flip-flop and the output signal of the corresponding flip-flop, for delivering; as the interior-division control signal, the output signal of the first flip-flop and the output signals of the OR gates corresponding to the flip-flops from the second onward.
In the present invention, the interpolator includes a logic circuit, which has at least first and second input terminals and one output terminal, for outputting result of a predetermined logical operation between first and second input signals that enter from the first and second input terminals; a first switch element, connected between a first power supply and an internal node, having a control terminal for receiving the output signal of the logic circuit; and a buffer circuit, which has an input terminal connected to the internal node, for inverting an output logic value if the size relationship between potential at the internal node and a threshold value reverses; wherein a plurality of series circuits are connected in parallel between the internal node and a second power supply and each series circuit comprises a first constant-current source, a second switch element turned on and off by the first input signal, and a third switch element turned on and off by the interior-division control signal from the interpolator control circuit, and a plurality of series circuits are connected in parallel between the internal node and the second power supply and each series circuit comprises a second constant-current source, a fourth switch element turned on and off by the second input signal, and a fifth switch element turned on and off by the interior-division control signal from the interpolator control circuit.
In the present invention, the interpolator has a first switch element group and a second switch element group stacked one above the other between a high-potential power supply and an internal node, wherein the first switch element group, which is composed of parallel switch elements, has the input signal from the first input terminal or a signal that is the inverse of this input signal input commonly to control terminals thereof and the second switch element group, which is composed of parallel switch elements, has the interior-division ratio control signal input to respective ones of the control terminals thereof; a third switch element group and a fourth switch element group stacked one above the other between the internal node and a low-potential power supply, wherein the third switch element group, which is composed of parallel switch elements, has the interior-division ratio control signal input to respective ones of the control terminals thereof and the fourth switch element group, which is composed of parallel switch elements, has the input signal from the second input terminal or a signal that is the inverse of this input signal input commonly to control terminals thereof; a fifth switch element group and a sixth switch element group stacked one above the other between the high-potential power supply and the internal node, wherein the fifth switch element group, which is composed of parallel switch elements, has the input signal from the second input terminal or a signal that is the inverse of this input signal input commonly to control terminals thereof and the sixth switch element group, which is composed of parallel switch elements, has a complementary signal of the interior-division ratio control signal input to respective ones of the control terminals thereof; and a seventh switch. element group and an eighth switch element group stacked one above the other between the internal node and the low-potential power supply, wherein the seventh switch element group, which is composed of parallel switch elements, has a complementary signal of the interior-division ratio control, signal input to respective ones of the control terminals thereof and the eighth switch element group, which is composed of parallel switch elements, has the input signal from the second input terminal or a signal that is the inverse of this input signal input commonly to control terminals thereof; a capacitor is connected between the internal node and the low-potential power supply; and a buffer circuit is-provided and has an input terminal connected to the internal node for inverting the output logic value if the size relationship between the potential at the internal node and a threshold value reverses.